1620 II

It had basic ALU hardware for addition and subtraction, but multiplication was still done by table lookup in Core memory. Multiplication used a 200 digit table (@ address 00100..00299). Rather than being an available option, as in the Model I, the Divide hardware using a repeated Subtraction algorithm, was built in. Floating Point arithmetic was an available option, as were Octal arithmetic and logic instructions.

The Core memory (@ address 00300..00399) that was freed by the replacement of the Addition table with hardware was used for storage of two selectable "bands" of seven (7) 5-digit index registers.

The console typewriter was replaced with a Selectric typewriter, which could type at 15 cps – a 50% improvement over the Model I.

The entire Core memory was in the IBM 1625 Memory unit. Memory cycle time was halved compared to the Model I's (internal or 1623 Memory unit), to 10μs (i.e., the cycle speed was raised to 100kHz) by using faster cores. A Memory Address Register Storage (MARS) Core memory read, clear, or write operation took 1.5μs and each write operation was automatically (but not necessarily immediately) preceded by a read or clear operation of the same "register(s)" during the 10μs Memory cycle.

The processor clock speed was also doubled, to 2MHz, which was still divided by 20 by a 10 position ring counter to provide the system timing/control signals.

The fetch/execute mechanism was completely redesigned, optimizing the timing and allowing partial fetches when the P or Q fields were not needed. Instructions took either 1, 4, or 6 Memory cycles (10μs, 40μs, or 60μs) to fetch and a variable number of Memory cycles to execute. Indirect addressing added 3 Memory cycles (30μs) for each level of indirection. Indexed addressing added 5 Memory cycles (50μs) for each level of indexing. Indirect and Indexed addressing could be combined at any level of indirection or indexing.

External link

• System Reference Manual for the IBM 1620 Central Processing Unit, Model 2